# 时钟控制器 CCM arch/arm/include/asm/arch-sunxi/clock_sun6i.h ~~~ struct sunxi_ccm_reg { u32 pll1_cfg; /* 0x00 pll1 control CPU*/ u32 reserved0; u32 pll2_cfg; /* 0x08 pll2 control AUDIO*/ u32 reserved1; u32 pll3_cfg; /* 0x10 pll3 control VIDEO*/ u32 reserved2; u32 pll4_cfg; /* 0x18 pll4 control VE*/ u32 reserved3; u32 pll5_cfg; /* 0x20 pll5 control DDR0*/ u32 reserved4; u32 pll6_cfg; /* 0x28 pll6 control PERIPH0*/ u32 reserved5; // 0x2C ISP u32 pll7_cfg; /* 0x30 pll7 control*/ u32 reserved6; u32 pll8_cfg; /* 0x38 pll8 control */ u32 reserved7; u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ u32 pll9_cfg; /* 0x44 pll9 control PERIPH1*/ u32 pll10_cfg; /* 0x48 pll10 control */ u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */ u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ u32 apb2_div; /* 0x58 APB2 divide ratio */ u32 axi_gate; /* 0x5c axi module clock gating */ u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ u32 apb1_gate; /* 0x68 apb1 module clock gating */ u32 apb2_gate; /* 0x6c apb2 module clock gating */ u32 bus_gate4; /* 0x70 gate 4 module clock gating */ u8 res3[0xc]; u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ u32 ts_clk_cfg; /* 0x98 transport stream clock control */ u32 ss_clk_cfg; /* 0x9c security system clock control */ u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ u32 spi3_clk_cfg; /* 0xac spi3 clock control */ u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ u32 reserved10[2]; u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ u32 reserved11[2]; u32 usb_clk_cfg; /* 0xcc USB clock control */ u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ u32 reserved12[7]; u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */ u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */ u32 dram_clk_gate; /* 0x100 DRAM module gating */ #ifdef CONFIG_SUNXI_DE2 u32 de_clk_cfg; /* 0x104 DE module clock */ #else u32 be0_clk_cfg; /* 0x104 BE0 module clock */ #endif u32 be1_clk_cfg; /* 0x108 BE1 module clock */ u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ u32 mp_clk_cfg; /* 0x114 MP module clock */ u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ u32 reserved14[3]; u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ u32 ve_clk_cfg; /* 0x13c VE module clock */ u32 adda_clk_cfg; /* 0x140 ADDA module clock */ u32 avs_clk_cfg; /* 0x144 AVS module clock */ u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ u32 reserved15; u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ #ifdef CONFIG_SUNXI_DE2 u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ #else u32 ps_clk_cfg; /* 0x154 PS module clock */ #endif u32 mtc_clk_cfg; /* 0x158 MTC module clock */ u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ u32 reserved16; u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ u32 reserved17[4]; u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ u32 reserved18[4]; u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ u32 reserved19[21]; u32 pll_lock; /* 0x200 PLL Lock Time */ u32 pll1_lock; /* 0x204 PLL1 Lock Time */ u32 reserved20[6]; u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ u32 reserved21[5]; u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */ u32 reserved21_5[7]; u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */ u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */ u32 reserved22[3]; u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ u32 reserved23; u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ u32 reserved24; u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ u32 reserved25[5]; u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */ }; ~~~